This invention relates generally to exposure apparatus and methods and, more particularly, to an exposure method, an exposure apparatus, and a mask that are suitable for, for example, manufacturing an active matrix liquid crystal display (liquid crystal panel) having a switching device.
In recent years, a high-resolution color liquid crystal display (LCD) with a wide screen has been used as a display for personal computers or television sets. The screen size (screen diagonal) of a current LCD is typically 10-12 inches; however, a wide screen LCD with a 16-inch screen, 20-inch screen, or still wider screen, is being developed. In response to the increased screen size, the resolution is also improved, and an LCD having a VGA (640X480) pixel matrix, XGA (1024X768) pixel matrix, or SXGA (1280X1024) pixel matrix is being manufactured. An active matrix LCD is superior in the response characteristic of image display, wide view angle characteristics, and multi-tone characteristics. In many applications, a thin film transistor LCD (TFT/LCD), which uses a thin film transistor as a switching device in each pixel, has been used.
FIG. 16 illustrates an example of the pixel structure of a TFT/LCD in a conventional display device as an enlarged plan view, which shows a portion of the array substrate (on which TFTs are formed). A plurality of gate lines 132 are formed on the glass substrates 142 along the horizontal direction of a display screen, and a plurality of data lines 130 are formed in the vertical direction. Areas defined by the gate lines 132 and the data lines 130 are display pixel areas, in which a transparent pixel electrode 134 made of ITO (indium tin oxide) is formed. A gate electrode 136, which is derived from the gate line 132, is formed in a corner of each display area. A channel layer 144 made of, for example, amorphous silicon (.alpha.-Si) is formed on the gate electrode 136 with a gate insulation film (not shown) therebetween. A drain electrode 140, which is derived from the data line 130, and a source electrode 138, which is electrically connected to the transparent electrode 134, are formed on the channel layer 144 simultaneously. A TFT is composed of a gate electrode 136, a gate insulation film, a channel layer 144, and source and drain electrodes 136, 140.
The circuit pattern in each layer, which constitutes a TFT/LCD, is formed through a photolithographic process, in which a projection exposure apparatus is used to expose the circuit pattern formed on a photomask or reticle (collectively, referred to as a reticle) onto a resist layer (photosensitizer) formed on the glass substrate 142. The resist layer is developed and used as a mask on which the circuit pattern has been transferred. Using the photoresist mask, a semiconductor layer made of, for example, .alpha.-Si is etched to form the channel layer 144. The gate line 132, gate electrode 136, data line 130 and source/drain electrodes 138, 140 are formed by etching a metal interconnection layer.
There are two types of exposure apparatus, namely, a step-and-repeat-type and a scanning-type. In a scanning-type exposure apparatus, the reticle and the glass substrate are moved in synchronization with each other.
In a step-and-repeat-type apparatus, the photosensitive substrate (glass substrate) mounted on the movable stage is driven in a step-and-repeating manner to successively expose a portion of the reticle pattern onto a predetermined area on the photosensitive substrate in a section-by-section manner. In this type of exposure apparatus, a plurality of reticles are held in a reticle changer. The reticle changer and the stage are driven so as to successively expose a portion of the multiple reticle patterns onto one of the divided pattern areas on the photosensitive substrate, thereby forming a first layer. Other patterns on different reticles held in the reticle changer are subsequently exposed to form a second layer over the first layer.
FIG. 17 illustrates the first and second layers LY1 and LY2 exposed onto the photosensitive substrate P, which is mounted on the movable stage of an exposure apparatus. Unit patterns LY1A and LY1B of the first layer LY1 are exposed successively onto the photosensitive substrate P, and LY1A and LY1B are combined through a stitching portion JN. Similarly, unit patterns LY2A and LY2B of the second layer LY2 are successively exposed over the first layer, and LY2A and LY2B are combined through the stitching portion JN.
The movable stage (not shown in FIG. 17) that supports the photosensitive substrate P is moved within the X-Y plane in a controllable manner, and the position of the photosensitive substrate P mounted on the movable stage is controlled within the X-Y coordinate system. If, for example, the first unit pattern LY1A of the first layer LY1 is exposed onto the substrate with an offset of -.DELTA.x from the target exposure position, and the first unit pattern LY2A of the second layer LY2 is exposed with an offset of +.DELTA.x from the target exposure position, then the offset of the first pattern LY2A of the second layer LY2 becomes +2.DELTA.x relative to the first unit pattern LY1A of the first layer LY1, which corresponds to the distance between the exposure positions of LY1A and LY2A.
If the second unit pattern LY1B of the first layer LY1 is exposed with an offset of +.DELTA.x from the target exposure position, and the second unit pattern LY2B of the second layer LY2 is exposed with an offset of -.DELTA.x from the target exposure position, then the offset of the second unit pattern LY2B of the second layer LY2 becomes -2.DELTA.x relative to the second unit pattern LY1B of the first layer LY1, which is the distance between the exposure positions of LY1B and LY2B. Accordingly, the total offset of the second layer LY2 relative to the first layer LY1 becomes +4.DELTA.x with respect to the stitching JN, as shown in FIG. 18.
If such an offset occurs during the exposure process, in a thin film transistor of the liquid crystal panel, the drain electrode DR and the source electrode SO formed in the second layer LY2 are offset by +4.DELTA.x relative to the gate electrode GA formed in the first layer LY1, as shown in FIG. 19.
The hatched areas PIL1 and PIL2 of the drain electrodes DR, which overlap the gate electrodes GA, define the capacitor capacitance generated between the gate electrode GA and the drain electrode DR. Change in the capacitance results in variation in the holding voltage of the thin film transistor. If the overlapping areas PIL1 and PIL2 differ in the left and right sides of the liquid crystal panel with the stitching portion JN as a boundary, the light-permeability of the liquid crystal panel varies from area to area. Consequently, the contrast differs between the left and right halves of the liquid crystal panel, separated at the stitching portion JN.
As the glass substrate 142 is enlarged along with the increased size of TFT/LCDs, a scanning-type projection exposure apparatus with a plurality of projection lens systems has been preferably used to increase the projection exposure area of the apparatus. In such a scanning-type projection exposure apparatus, the circuit pattern on a reticle is divided into multiple trapezoid areas when exposed onto a glass substrate. The reticle and the glass substrate are synchronously scanned with respect to the projection lens systems. In this manner, the entire area of the reticle circuit pattern is transferred to the glass substrate.
FIG. 20(a) shows a portion of the projection area formed on the glass substrate 142 by a scanning-type projection exposure apparatus. The trapezoid projection areas 150, 152 formed through individual projection lens systems overlap each other in the Y direction by a predetermined amount. This arrangement enables the circuit pattern to be illuminated uniformly. In the figure, the glass substrate 142 moves in the X direction relative to the projection areas 150, 152. The range "b" (with a width of, for example, 5 mm) indicates the overlapping area of the projection areas 150 and 152 in the Y direction. The range "a" indicates the non-overlapping area of the projection area 150, while the range "c" indicates the non-overlapping area of the projection area 152.
In general, the imagery characteristics of a plurality of projection lens systems used in the scanning-type projection exposure system vary slightly. Suppose that the projection lens system used for image formation in the projection area 150 has an imagery characteristic that causes the image-forming position to shift .DELTA.P in the -Y direction (as indicated by the left arrow in FIG. 20(a) ), and further suppose that the projection system used for image formation in the projection areas 152 has an imagery characteristic that causes the image-forming position to shift .DELTA.P in the +Y direction (as indicated by the right arrow), then overlay errors occur, as shown in FIG. 20, between the layers exposed by the projection lens systems that have characteristics different from each other. In FIG. 20, the horizontal axis represents a Y position, and the vertical axis represents an error with respect to the designated pattern-forming position in the layers. The positional errors in the areas "a" and "c" are .DELTA.P with opposite signs, and therefore, the total offset between the areas "a" and "c" becomes 2.DELTA.P. In the area "b", the exposure ratio of the projection area 150 to the area 152 changes linearly, and the offset of the formed pattern also changes linearly from -.DELTA.P to +.DELTA.P. In this context, the area in which two projection areas are overlapped during exposure is called the "stitching portion".
If the imagery characteristics of multiple projection lens systems of a scanning-type exposure apparatus vary slightly, the magnitudes and the directions of offset of the pattern images formed through these projection lens systems also vary with respect to the stitching portion.
Generally, a plurality of scanning-type projection exposure apparatus are used in the photolithographic process, each apparatus being used to expose one of the layers of a TFT. Accordingly, the accuracy in overlaying a plurality of layers may be adversely affected by variation in the imagery characteristics of the different scanning-type projection exposure apparatus. In addition, variation in the imagery characteristics of the multiple projection lens systems provided in a scanning-type projection exposure apparatus may also affect the overlay accuracy.
FIGS. 21(a)-(c) show overlay errors in overlaid layers, which are caused when a layer of the gate line and gate electrode of a TFT and a layer of the data line and source/drain electrodes of the TFT are formed by separate scanning-type projection exposure apparatus.
FIG. 21(a) is similar to FIG. 20(a) and shows the overlapping area between the projection areas 150 and 152 in which a data line and source/drain electrodes (collectively referred to as source/drain electrodes) are formed as a first layer by the first scanning-type projection exposure apparatus. FIG. 21(b) shows the overlapping area between projection areas 154 and 156 in which a gate line and a gate electrode (collectively referred to as a gate electrode) are formed as a second layer on the glass substrate 142 by the second scanning-type projection exposure apparatus. The imagery characteristic of the projection lens system that forms a pattern image in the projection area 154 causes the image-forming position to shift .DELTA.P in the +Y direction, as indicated by the right arrow. On the other hand, the imagery characteristic of the projection lens system that forms a pattern image in the projection area 156 causes the image-forming position to shift .DELTA.P in the -Y direction, as indicated by the left arrow.
For purposes of illustration, FIGS. 21(a) and 21 (b) depict the case in which the possible overlay error becomes largest because the upper layer is exposed by a projection lens system that has an imagery characteristic opposite to that of the projection lens system for exposing the lower layer.
FIG. 21(c) shows overlay errors that occur when the lower layer gate electrode is formed on the glass substrate through the second scanning-type projection exposure apparatus, and then the upper layer source/drain electrodes are formed over the lower layer through the first scanning-type projection exposure apparatus. The horizontal axis represents a Y position, and the vertical axis represents an error.
The dashed line A indicates the positional shift of the gate electrode formed in the lower layer, and the solid line B indicates the positional shift of the source/drain electrodes formed in the upper layer. The bold solid line C indicates the overlay error (C=B-A) between the gate electrode and the source/drain electrodes. The overlay error equals the offset of the upper source/drain electrodes relative to the lower gate electrode. Therefore, the overlay error of the source/drain electrodes with respect to the gate electrode becomes -2.DELTA.P in the area a. The overlay error of the source/drain electrodes with respect to the gate electrode becomes 2.DELTA.P in the area c. The overlay error in the area b, in which the gate electrode layer and the source/drain layer overlap each other, changes linearly from -.DELTA.P to +.DELTA.P, because the positional shifts of the gate electrode pattern and source/drain pattern change linearly, as mentioned above. Consequently, the largest possible overlay error in the area b is 4.DELTA.P.
FIGS. 22(a)-(c) illustrate the aforementioned overlay error more concretely, showing the positional shift of the source/drain electrodes 138, 140 that overlap the gate electrode 136 in each TFT area of a TFT/LCD formed by the projection exposure method. FIG. 22(a) shows the overlay error of the source/drain electrodes 138, 140 with respect to the gate electrode 136 in the area "a". The dashed line indicates the originally designed pattern-forming positions of the layers. Relative to the reference positions defined by the dashed line, the formed gate electrode 136 is offset in the +Y direction, while the formed source/drain electrodes 138, 140 are offset in the -Y direction. Similarly, FIG. 22(c) shows the overlay error of the source/drain electrodes 138, 140 with respect to the gate electrode 136 in the area "c". The gate electrode 136 is formed offset in the -Y direction, while the source/drain electrodes 138, 140 are formed offset in the +Y direction. Concerning the area "b" in which the patterns formed in the areas "a" and "c" overlap each other in a stitching portion, the overlay error of the upper layer with respect to the lower layer becomes small in the vicinity of the center. Near the edge portions of the area "b", however, the overlay error in the area "b" comes close to the error rate in the area "a" or "c".
In summary, a plurality of scanning-type projection exposure apparatus are used in the ordinary exposure process for manufacturing an LCD to expose and form patterns in the respective layers. Because each layer is formed through a different exposure apparatus, the overlaying accuracy of each layer is greatly affected by variations in the imagery characteristics of different projection lens systems used in the projection exposure apparatus, or by variations in the imagery characteristics of the plurality of projection exposure apparatus used in the exposure process.
In manufacturing a TFT, if the overlapping area of the source electrode that covers the gate electrode changes, the parasitic capacitance between the source electrode and the gate electrode also changes, which further affects the characteristics of the TFT element. The change in the TFT element characteristics results in flickers or burning in the LCD screen.
It is clear from FIG. 21 that if the overlay error rate varies steeply in the stitching portion of area "b" in which two projection areas overlap each other, then the TFT element characteristics that are located on both sides of the stitching portion differ greatly from each other. Consequently, the difference will be visually recognized as unevenness or deterioration of the image quality with the stitching portion as a boundary. This phenomena is called "screen separation" or "uneven split".